Eby Friedman

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Eby G. Friedman
Born	1 January 1957 (age 67) Jersey City, New Jersey
Alma mater	University of Rochester
Awards	Charles A. Desoer Technical Achievement Award (2013) [1]
Scientific career
Fields	Electrical and Computer Engineering
Institutions

Eby G.Friedman is a Fellow of the IEEE ^[2] and Professor at the University of Rochester in the field of: electronic imaging system ,high performance VLSI/IC design and analysis, synchronous digital microelectronic design, synchronous mixed signal microelectronic design (with application to high speed portable processors and low power wireless communications) Professor Friedman is also a Visiting Professor at the Technion - Israel Institute of Technology, and directs the Technion Advanced Circuits Research Center (ACRC).
Born in Jersey City, New Jersey in 1957 he received the Ph. D. degrees from the University of California, Irvine, in electrical engineering. Since 1978 Under the employment of Hughes Aircraft Company .he worked on the design of bipolar differential amplifiers, the development of supporting design and test methodologies and CAD tools, functional and parametric test, and the development of high performance and high resolution DSP and oversampled systems. Afterwards he resigned to the Academy
Professor Eby is married to Laurie Friedman and they have 2 kids

High Performance Digital and Analog VLSI/ICs

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The focus of this research is the design and analysis of high performance digital and analog integrated circuits, and supporting design techniques, methodologies, CAD tools, and circuit structures. Speed, area, power dissipation, and reliability trade offs in CMOS technology are investigated in terms of application-specific constraints and their fundamental circuit level limitations. The general approach is to apply analog signal concepts to the design and analysis of VLSI systems to maximize both circuit and system level performance while satisfying the complexity requirements inherent to the VLSI environment.

On-Chip Interconnect and Substrate Coupling Noise

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Interconnect and substrate coupling noise have become issues of primary concern in high speed digital and mixed-signal integrated circuits. In order to ascertain whether a section of interconnect should be modeled as either an RC or an RLC impedance, figures of merit are being developed to determine how best to model both a line and a tree. Closed form solutions characterizing the propagation delay, rise time, overshoots, and settling time of signals in an RLC tree and the peak coupling noise voltage (or crosstalk) between adjacent RLC interconnect are also under development. Substrate coupling between high current analog devices and digital latches is under investigation based on simulation and extensive data derived from experimental test circuits. The focus of these research efforts is on interpreting, designing, and compensating for the effects of RLC interconnect and substrate impedances rather than extraction and simulation algorithms. Particular effort is being placed on the on-chip global signals, such as the clock and power distribution networks and the interactions of these networks with the substrate, neighboring interconnect, and the on-chip decoupling capacitors.

Automated Synthesis of High Performance Clock Distribution Networks

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Most ULSI/VLSI-based systems utilize fully synchronous timing, requiring a globally distributed clock signal as a temporal reference signal to control the sequence of operations. This high speed clock signal must be distributed to every register at a precise time. The focus of this research is the automated synthesis of high speed, highly reliable clock distribution networks. A four phase top-down design system is under development for synthesizing buffered clock distribution networks. This capability will be developed as an integrated synthesis system, validated with benchmark circuits, and tested with manufactured demonstration circuits.

Circuit Design Techniques for Driving RLC Interconnect

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Interconnect impedances have become the predominant source of delay in deep submicrometer CMOS circuits. The interaction between the active CMOS transistors and the passive interconnect is a fundamental issue in the design of high performance VLSI-based systems. Furthermore, the interconnect structure propagating high speed signals over long distances is properly modeled as an RLC transmission line. The focus of this research effort is on the development of closed form and accurate analytic expressions that describe the interaction between the CMOS circuits and the interconnect impedances loading these transistors. These expressions are applied to the development of VLSI-based design methodologies for driving these RC and RLC interconnect impedances.

Integrated Pipelining, Retiming, and Clock Scheduling

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For the optimal behavioral synthesis of a synchronous system, the processes of pipelining, retiming, and clock skew scheduling must be implemented in an integrated fashion. Physically accurate algorithms are being developed to more efficiently synthesize these high performance synchronous systems. These results will provide a systematic procedure for building high performance recursively structured pipelined systems and related clock distribution networks.

Design of MSI/LSI Circuits Based on Innovative Technologies

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Specialized circuits using aggressive niche technologies are developed by applying innovative design techniques and specialized CAD tools. This research area requires a merging of a materials/device background with practical circuit design issues when building extremely high performance systems (i.e., high speed, low power, mixed signals, low noise.)

• Fellow of the IEEE^[3]
• Chair of the steering committee for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems ^{[citation needed]}
• Regional Editor of the [[Journal of Circuits, Systems and Computers^[4]
• Member of the editorial board of the [[Analog Integrated Circuits and Signal Processing^[5]
• Member of the editorial board of the Microelectronics Journal ^{[citation needed]}
• Member of the editorial board of the Journal of Low Power Electronics ^{[citation needed]}
• Member of the editorial board of the Journal of VLSI Signal Processing ^{[citation needed]}
• Member of the technical program committee of a number of conferences ^{[citation needed]}
• Distingushed Lecturer of the IEEE CAS Society ^{[citation needed]}
• Member of the editorial board of the Proceedings of the IEEE and IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing ^{[citation needed]}
• Member of the IEEE Circuits and Systems (CAS) Society Board of Governors,CAS liaison to the IEEE Solid-State Circuits Society (SSCS) ^{[citation needed]}
• Guest editor of several special journal issues ^{[citation needed]}
• Chair of the VLSI Systems and Applications IEEE Circuits and Systems Society Technical Committee^[6]
• Chair of the Electron Devices Chapter of the IEEE Rochester Section ^{[citation needed]}
• General/Program/Technical Co-Chair of the 1997 International Workshop on Clock Distribution Networks ^{[citation needed]}
• Chair of the 2000 IEEE Workshop on Signal Processing Systems ^{[citation needed]}
• Chair of the 2003 and 2004 IEEE International Workshop on System-on-Chip for Real-Time Applications ^{[citation needed]}
• Chair of the 2004 IEEE International Conference on Electronics, Circuits, and Systems ^{[citation needed]}
• Chair of the 2006 IEEE International Symposium on Circuits and Systems^[7]
• Chair of the 2007 IEEE International Symposium on Networks on Chip (NoC) ^{[citation needed]}

Personal Awards

• Charles A. Desoer Technical Achievement Award 2013 ^{[citation needed]}
• Fulbright Fellowship: 2000-2001 ^{[citation needed]}
• Distingushed Lecturer of the IEEE CAS Society: 2000-2001 ^{[citation needed]}
• IEEE Fellow: 2000 - "For contributions to high performance circuit design and VLSI-based synchronous systems." ^{[citation needed]}
• IBM University Research Award: 1997 ^{[citation needed]}
• GRC Inventor Recognition Award ^{[citation needed]}
• Outstanding Chapter Chairman for IEEE Rochester Section: 1996 ^{[citation needed]}
• University of Rochester Engineering College Teaching Excellence Award: 1994 ^{[citation needed]}
• DoD Augmentation Award for Science and Engineering Research Training: 1993 ^{[citation needed]}
• NSF Research Initiation Award: 1992 ^{[citation needed]}
• Howard Hughes Doctoral Fellowship: 1986-1989 ^{[citation needed]}
• Howard Hughes Masters Fellowship: 1980-1981 ^{[citation needed]}

Group Awards

• Shahar Kvatinsky with Uri Weiser, Avinoam Kolodny, and Eby G. Friedman received the 2015 IEEE Circuits and Systems Society Guillemin-Cauer Best Paper Award^[8] for our paper, " TEAM – ThrEshold Adaptive Memristor Model"^[9] published in the IEEE Transactions on Circuits and Systems I: Regular Papers in January 2013.

• Eby G. Friedman received the " IEEE Circuits and Systems 2013 Charles A. Desoer Technical Achievement Award".^[10]

• Shahar Kvatinsky with Uri Weiser, Avinoam Kolodny, and Eby G. Friedman, received the 2013 Sanford Kaplan Prize for Creative Management in High Tech in the 21st Century. ^{[citation needed]}

• The paper by Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, and Avinoam Kolodny, " Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect,"^[11] published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems in May 2010 won the 2012 IEEE Circuits and Systems Society VLSI Transactions Best Paper Award.^[12]

• The paper by Vasilis F. Pavlidis and Eby G. Friedman, " 3-D Topologies for Networks-on-Chip,"^[13] published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems in October 2007 is on the list of Top 25 Downloaded Manuscripts^[14] for this journal in 2009.

• The paper by Mikhail Popovich and Eby G. Friedman, " Decoupling Capacitors for Multi-Voltage Power Distribution Systems,"^[15] published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems in March 2006 is on the list of Top 25 Downloaded Manuscripts^[16] for this journal in 2007.

• The paper by Guoqing Chen and Eby G. Friedman, " An RLC Interconnect Model Based on Fourier Analysis,"^[17] published in the IEEE Transactions on Computer-Aided Design in February 2005 is on the list of Top Downloaded Papers in 2005 for this journal.

• Vasilis Pavlidis received the AMD/CICC Student Scholarship Award for his paper, "Clock Distribution Networks for 3-D Integrated Circuits," with E. G. Friedman at the 2008 IEEE Custom Integrated Circuits Conference. ^{[citation needed]}

• Ioannis Savidis' paper at the 2008 IEEE International Symposum on Circuits and Systems in Seattle, Washington was a finalist for the student best paper award for the paper, I. Savidis and E. G. Friedman, " Electrical Characterization and Modeling of 3-D Vias,"^[18] Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 784 – 787. May 2008.

• Mikhail Popovich and Eby G. Friedman received the GRC Inventor Recognition Award in 2007 for their invention, "Placement of On-Chip Decoupling Capacitors." ^{[citation needed]}

• The paper by Volkan Kursun and our Intel collaborators, Siva G. Narendra and Vivek K. De, " Low-Voltage-Swing Monolithic dc-dc Conversion,"^[19] published in the IEEE Transactions on Circuits and Systems II: Express Briefs in May 2004, is on the list of Top 15 Downloaded Papers for this journal in both 2004 and 2005.

• Emre Salman's paper at the 2006 IEEE International Symposum on Quality Electronic Design in San Jose, California was nominated for the best paper award for the paper, E. Salman, A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman, " Pessimism Reduction in Static Timing Analysis Using Interdependent Setup and Hold Times,"^[20] Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 159–164, March 2006.

• Eby G. Friedman received the " University Award for Excellence in Graduate Teaching"^[21] on May 14, 2005 from the University of Rochester.

• Mikhail Popovich received the Best Student Paper Award at the 2005 ACM Great Lakes Symposium on VLSI in Chicago, Illinois for the paper, M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, " On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits,"^[22] Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 2–7, April 2005.

• Boaz Shem-Tov's paper at the 2004 IEEE International Conference on Electronics, Circuits and Systems in Tel Aviv, Israel was a best paper finalist for the paper, B. Shem-Tov, M. Kozak, and E. G. Friedman, " A 250 MHz Delta-Sigma Modulator for Low Cost Ultrasound/Sonar Beamforming Applications,"^[23] Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 113–116, December 2004.

• Dimitris Velenis received the 2004 EDAA Outstanding Dissertation Award in the category: "New Directions in Physical Design Automation," awarded by the European Design and Automation Association (EDAA) for his Ph.D. dissertation, Delay Uncertainty in High Performance Clock Distribution Networks.^[24]

• Yehea Ismail won the 2002 IEEE Circuits and Systems Outstanding Young Author Award for the paper, Y. I. Ismail and E. G. Friedman, " Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits,"^[25] IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 2, pp. 195–206, April 2000.

• Clock Distribution Networks in VLSI Circuits and Systems (IEEE Press, 1995)^[26]
• High Performance Clock Distribution Networks (Kluwer Academic Publishers, 1997)^[27]
• Analog Design Issues in Digital VLSI Circuits and Systems (Kluwer Academic Publishers, 1997)^[28]
• Timing Optimization through Clock Skew Scheduling (Kluwer Academic Publishers, 2000 and 2009)

(first and second edition) ^{[citation needed]}

• On-Chip Inductance in High Speed Integrated Circuits (Kluwer Academic Publishers, 2001)^[29]
• Power Distribution Networks in High Speed Integrated Circuits (Kluwer Academic Publishers, 2004)^[30]
• Multi-Voltage CMOS Circuit Design (John Wiley & Sons Press, 2006)^[31]
• Power Distribution Networks with On-Chip Decoupling Capacitors (Springer Verlag, 2008 and 2011)

(first and second edition) ^{[citation needed]}

• Three-Dimensional Integrated Circuit Design (Morgan Kaufmann, 2009) ^{[citation needed]}
• High Performance Integrated Circuit Design (McGraw-Hill Publishers, 2012) ^{[citation needed]}
• J. Rosenfeld and E. G. Friedman, On-Chip Resonance in Nano scale Integrated Circuits: Design and Analysis Methodologies for Advanced Data, Clock, and Power Generation Networks(Lambert Academic Publishing) ^{[citation needed]}
• D. Velenis and E. G. Friedman, Delay Uncertainty in High Performance Clock Distribution Networks Issues and Solutions(Lambert Academic Publishing) ^{[citation needed]}
• M. El-Moursy and E. Friedman, On-Chip Inductive Interconnect Design Methodologies ^{[citation needed]}

• Professor Friedman also published over 270 papers in fields of high speed and low power CMOS design techniques, interconnect and substrate noise, pipelining and retiming, three-dimensional integration, and the theory and application of power and synchronous clock distribution networks. ^{[citation needed]}

United States Patents

• S. Kose and E. G. Friedman, " Digitally Controlled Wide Range Pulse Width Modulator " United States Patent, No. 9,007,140, April 14, 2015.^[32]
• A. Morgenshtein, R. Ginosar, A. Kolodny, and E. G. Friedman, " Logic Circuit Delay Optimization," United States Patent, No. 8,225,265, July 17, 2012.^[33]
• E. G. Friedman and G. Chen, " Transient Response of a Distributed RLC Interconnect based on Direct Pole Extraction," United States Patent, No. 7,818,149 B2, October 19, 2010.^[34]
• M. Popovich and E. G. Friedman, " Method for Effective Placement of On-Chip Decoupling Capacitors Determined by Maximum Effective Radii," United States Patent, No. 7,802,220 B1, September 21, 2010.^[35]
• M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, " Method and Apparatus to Reduce Noise Fluctuation in On-Chip Power Distribution Networks," United States Patent, No. 7,595,679 B1, September 29, 2009.^[36]
• V. Kursun and E. G. Friedman, " Domino Logic with Variable Threshold Voltage Keeper," United States Patent, No. 7,388,399 B1, June 17, 2008.^[37]
• V. Kursun and E. G. Friedman, " Domino Logic with Variable Threshold Voltage Keeper," United States Patent, No. 7,218,151 B1, May 15, 2007.^[38]
• J. Rosenfeld, M. Kozak, and E. G. Friedman, " High-Gain, Bulk-driven Operational Amplifiers for System-on-chip Applications," United States Patent, No. 7,088,178 B1, August 8, 2006.^[39]
• V. Kursun and E. G. Friedman, " Dual Threshold Voltage and Low Swing Domino Logic Circuits," United States Patent, No. 6,900,666, May 31, 2005.^[40]
• Y. Ismail and E. G. Friedman, " Model for Simulating Tree Structured VLSI Interconnect," United States Patent, No. 6,460,165, October 1, 2002.^[41]
• E. Friedman and R. M. Secareanu, " Digital CMOS Voltage Interface Circuits," United States Patent, No. 6,366,127, April 2, 2002.^[42]
• E. Friedman and R. M. Secareanu, " Current Mirror and/or Divider Circuits with Dynamic Current Control which are Useful in Applications for Providing Series or Reference Currents, Subtraction, Summation and Comparison," United States Patent, No. 6,166,590, December 26, 2000.^[43]
• E. Friedman and R. M. Secareanu, " Digital Buffer Circuits," United Sates Patent, No. 6,163,174, December 19, 2000.^[44]

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